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2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
PRECHARGE Command
Figure 49: READ Burst Followed by PRECHARGE – RL = 3, BL = 4, RU( t RTP(MIN)/ t CK) = 3
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
BL/2
RL = 3
CA[9:0]
Bank m
col addr a Col addr a
t RTP
=3
Bank m
t RP
Bank m
row addr
Row addr
CMD
READ
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVATE
NOP
NOP
DQS#
DQS
DQ
D OUT A0
D OUT A1
D OUT A2
D OUT A3
Transitioning data
WRITE Burst Followed by PRECHARGE
For WRITE cycles, a WRITE recovery time ( t WR) must be provided before a PRECHARGE
command can be issued. t WR delay is referenced from the completion of the burst
WRITE. The PRECHARGE command must not be issued prior to the t WR delay. For
WRITE-to-PRECHARGE timings see Table 43 (page 73).
These devices write data to the array in prefetch quadruples (prefetch = 4). An internal
WRITE operation can only begin after a prefetch group has been completely latched.
The minimum WRITE-to-PRECHARGE time for commands to the same bank is WL +
BL/2 + 1 + RU( t WR/ t CK) clock cycles. For untruncated bursts, BL is the value set in the
mode register. For truncated bursts, BL is the effective burst length.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
70
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
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MT42L256M32D4KP-MS
制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk